VLSI IEEE Project 2014-2015
VLSI IEEE PROJECTs TITLE 2014-2015
|
Sl. No |
TITLE |
YEAR |
| 1 | Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding | 2014-15 |
| 2 | Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding | 2014-15 |
| 3 | Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection | 2014-15 |
| 4 | Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes | 2014-15 |
| 5 | Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm | 2014-15 |
| 6 | Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms | 2014-15 |
| 7 | Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count | 2014-15 |
| 8 | Protein Alignment Systolic Array Throughput Optimization | 2014-15 |
| 9 | Quaternary Logic Lookup Table in Standard CMOS | 2014-15 |
| 10 | Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. | 2014-15 |
| 11 | A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler | 2014-15 |
| 12 | Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. | 2014-15 |
| 13 | A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler | 2014-15 |
| 14 | Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache | 2014-15 |
| 15 | A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS | 2014-15 |
| 16 | A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme | 2014-15 |
| 17 | A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits | 2014-15 |
| 18 | A Low Complexity-High Throughput QC-LDPC Encoder | 2014-15 |
| 19 | A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures | 2014-15 |
| 20 | A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain | 2014-15 |
| 21 | A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture | 2014-15 |
| 22 | A Synergetic Use of Bloom Filters for Error Detection and Correction | 2014-15 |
| 23 | Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC | 2014-15 |
| 24 | Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms | 2014-15 |
| 25 | An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS | 2014-15 |
| 26 | An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability | 2014-15 |
| 27 | Analysis and Characterization of Capacitance Variation Using Capacitance Measurement Array | 2014-15 |
| 28 | Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit | 2014-15 |
| 29 | Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter | 2014-15 |
| 30 | Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation | 2014-15 |
| 31 | Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation | 2014-15 |
| 32 | Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane | 2014-15 |
| 33 | Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging | 2014-15 |
| 34 | Design Techniques to Improve Blocker Tolerance of Continuous-Time __ ADCs | 2014-15 |
| 35 | Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor | 2014-15 |
| 36 | Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three | 2014-15 |
| 37 | Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects | 2014-15 |
| 38 | Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems | 2014-15 |
| 39 | Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers | 2014-15 |
| 40 | Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories | 2014-15 |
| 41 | Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs | 2014-15 |
| 42 | Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study | 2014-15 |
| 43 | Fast Radix-10 Multiplication Using Redundant BCD Codes | 2014-15 |
| 44 | Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint | 2014-15 |
| 45 | Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} | 2014-15 |
| 46 | Fault Tolerant Parallel Filters Based on Error Correction Codes | 2014-15 |
| 47 | Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis | 2014-15 |
| 48 | Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications | 2014-15 |
| 49 | Functional Constraint Extraction From Register Transfer Level for ATPG | 2014-15 |
| 50 | Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems | 2014-15 |
| 51 | Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs | 2014-15 |
| 52 | Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution | 2014-15 |
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Technologies used in VLSI
I Modelsim 6.5b Simulator
II Xilinx ISE 10.1 System generator
III Quartus 11.1
Tanner v7 EDA tool
1 S-Edit
2 T-spice
3 W-Edit
IV Microwind & DSCH v2
V H-spice
VI P-spice
VII LT-spice
VIII FPGA
1 Spartan IIIe
2 Altera DE2
IX Hardware Description Language
1 Verilog HDL
2 VHDL
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