Vlsi IEEE Projects 2015-2016

Vlsi IEEE Projects Titles 2015-2016

VLSI IEEE Projects 2015-2016

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S.NO	TITLE	CODE
1	A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator	LM_VL015_01
2	A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT	LM_VL015_02
3	A Class of SEC-DEDDAEC Codes Derived From Orthogonal Latin Square Codes	LM_VL015_03
4	Design of Efficient Content Addressable Memories in High-Performance FinFET Technology	LM_VL015_04
5	A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques	LM_VL015_05
6	A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process	LM_VL015_06
7	Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit	LM_VL015_07
8	Obfuscating DSP Circuits via High-Level Transformations	LM_VL015_08
9	Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms	LM_VL015_09
10	Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging	LM_VL015_10
11	ALevel-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs	LM_VL015_11
12	All Digital Energy Sensing for Minimum Energy Tracking	LM_VL015_12
13	Recursive Approach to the Design of a Parallel Self-Timed Adder	LM_VL015_13
14	Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications	LM_VL015_14
15	Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application	LM_VL015_15
16	FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems	LM_VL015_16
17	Algorithm and Architecture Design of the H.265/HEVC Intra Encoder	LM_VL015_17
18	Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding	LM_VL015_18
19	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications	LM_VL015_19
20	A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design, Modeling, and Simulation	LM_VL015_20
21	High-Throughput LDPCDecoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule	LM_VL015_21
22	A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography	LM_VL015_22
23	Graph-Based Transistor Network Generation Method for Supergate Design	LM_VL015_23
24	A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications	LM_VL015_24
25	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication	LM_VL015_25
26	Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications	LM_VL015_26
27	A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders	LM_VL015_27
28	Comparative Performance Analysis of the Dielectrically Modulated FullGate and Short-Gate Tunnel FET-Based Biosensors	LM_VL015_28
29	An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis	LM_VL015_29
30	VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm	LM_VL015_30
31	Fine-Grained Access Management in Reconfigurable Scan Networks	LM_VL015_31
32	A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors	LM_VL015_32
33	Partially Parallel Encoder Architecture for Long Polar Codes	LM_VL015_33
34	Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications	LM_VL015_34
35	One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes	LM_VL015_35
36	A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications	LM_VL015_36
37	A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling	LM_VL015_37
38	Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic	LM_VL015_38
39	Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations	LM_VL015_39
40	Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications	LM_VL015_40